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STV1601A serial interface transmission encoder november 1992 28 29 30 31 32 33 34 35 18 17 16 15 14 13 12 11 10 27 26 25 24 23 22 21 20 19 36 123456789 37 v ee d3x d4y d4x d5y d5x d6y d6x d7y d7x nc pck tn1 trp fv gnd pcy pcx rse v cc v ee d0y d0x d1y d1x d2y d2x d3y lst gnd sx sy gnd d9x d9y d8x d8y 1601a-01.eps pin connections pga37 (ceramic package) order code : STV1601A this ic contains all the circuits needed for conversion from parallel data, and parallel clock, into serial data. applications are straightforward as only a few external components are needed. other related ics include : . stv1602a, a serial transmission de- coder (with a built-in cable equal- izer and parallel-to-serial conversion) . stv1389aq coaxial cable driver structure . hybrid ic applications serial data transmission encoder . 100 to 270 mb/s applications examples . serial data transmission of digital television signal 525-625 lines . 4:2:2 component 270mb/s (10-bit) . 4*fsc pal composite 177mb/s (10-bit) . 4*fsc ntsc composite 143mb/s (10-bit) functions . parallel-to-serial conversion . scrambler : modulo - 2 division by g(x) = (x 9 + x 4 + 1) (x + 1) . pll for serial clock generation . pll lock detection . sync word required with the parallel data stream 8 bit 10 bit 1st word ffh 3ffh 2nd word 00h 000h 3rd word 00h 000h sync word conversion (8-bit timing reference signal is internally converted to 10-bit). code limitation the word composing the sync word listed above shall not appear during data words. this limitation includes 00 and ff in 8-bit use and 000 through 003 and 3fc through 3ff in 10-bit use. description the STV1601A is a hybrid ic encoder that converts parallel data into serial data for a serial transmis- sion line. 1/17
pin description pin n symbol equivalent circuit description i/o standard min. typ. max. unit 1 lst pll lock detection. is high while pll locked. if unlocked, becomes irregular. at free running (tn1 h) turns low h l o -1.0 -4.0 v v 36 pck clock output frequency divided to 1/10 vco output. used to check vco free running frequency h l o -0.8 -1.6 v v 3 sx differential serial output input parallel data is converted to serial, then from scrambled nrz to nrzi data h l o -1.6 -2.4 v v 4sy 1601a-01.tbl 1 v cc gnd 2k w 4k w 2k w ee v 1601a-02.eps gnd ee v 36 600 w 600 w 240 w 1601a-03.eps gnd v cc v cc 3 4 ee v v r3 30 w 100 w 100 w 30 w 2k w 2k w 115 w 1601a-04.eps STV1601A 2/17
pin description (continued) pin n symbol equivalent circuit description i/o standard min. typ. max. unit 29 v cc parallel data and clock input buffers power supply. when this pin is connected to +5v, parallel data clock turns to ttl mode. when this pin is connected to gnd, parallel data clock turns to ecl mode. - 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 d9x d9y d8x d8y d7x d7y d6x d6y d5x d5y d4x d4y d3x d3y d2x d2y d1x d1y d0x d0y parallel input ports: lsb : d0x or y msb : d9x or y signal : dnx return : dny for ecl mode, v cc shalll be 0v h l forttl mode, vcc shall be +5v h l -1.0 2.0 -1.6 0.8 v v v v 28 rse vco range selection h : high range 140 to 270mhz l : low range 100 to 145mhz h l i -0.4 -4.0 v v 1601a-02.tbl ee v 29 6 7 2k w 1k w v r3 1601a-05.eps gnd ee v 28 70k w 2k w 10k w 10k w 1601a-06.eps STV1601A 3/17
pin description (continued) pin n symbol equivalent circuit description i/o standard min. typ. max. unit 30 pcx parallel clock (pcx) and its return (pcy) for ecl mode, v cc = 0 h l for ttl mode, v cc = +5v h l i -1.0 2.0 -1.6 0.8 v v v v 31 pcy 2, 5, 32 gnd gnd 26 v ee -5v power supply i/o buffer pll -5.2 -5.0 -4.8 v 27 v ee -5v power supply logic part -5.2 -5.0 -4.8 v 33 fv vco free running frequency adjustment : v ee level gives the lowest frequency. to adjust, set tn1 high. i -3.9 v 34 trp vco input and phase comparator output should be connected to a parallel clock frequency trap filter to minimize jitter o -3.2 v 35 tn1 test mode : high : vco free running condition (input disabled) low : normal mode (input enabled) i -1.0 -4.5 v v 1601a-03.tbl ee v 2k w v r3 30 31 v cc 2k w 2k w 1601a-07.eps gnd 34 33 ee v 1k w 1k w 1k w 1k w 1k w 10k w 0.1 m f v cc 0.022 m f v 9 2 m f 220 w 1601a-08.eps 1 v cc gnd ee v v r3 20k w 12k w 4k w 1601a-09.eps STV1601A 4/17
pll lock detector vco timing generator nrz ? nrzi 000hex detector phase detector 35 30 31 33 34 28 36 paralell to serial converter x + x + 1 scr amble r 94 1 3 4 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 29 27 26 32 5 2 37 n.c. gnd gnd gnd v ee v ee cc v pcy pcx tn1 fv trp rse pck lst sx sy d9x d9y d8x d8y d7x d7y d6x d6y d5x d5y d4x d4y d3x d3y d2x d2y d1x d1y d0x d0y parallel clock serial clock parallel load 10-bit x 3 word shift register 1601a-10.eps block diagram absolute maximum ratings symbol parameter value unit v ee supply voltage -6 v v cc supply voltage +6 v v in input voltage v ee to v cc v i out output current -30 ma t oper operating temperature 0 to 65 o c t stg storage temperature -50 to 125 o c p d allowable power dissipation 2.0 w 1601a-04.tbl recommended operating conditions symbol parameter value unit v ee supply voltage -4.8 to -5.2 v v cc supply voltage * 4.8 to 5.2 v t oper operating temperature 0 to 65 o c * for ttl input. voltages are given with respect to gnd 1601a-05.tbl electrical characteristics (v ee = -5v, v cc = gnd/+5v, t a = 25 o c unless otherwise speciied) symbol parameter test conditions test circuit min. typ. max. unit dc characteristics i ee supply current 1 figure 2 140 ma i cc supply current 2 7 ma 1601a-06.tbl STV1601A 5/17
electrical characteristics (v ee = -5v, v cc = gnd/+5v, t a = 25 o c unless otherwise speciied) symbol parameter test conditions test circuit min. typ. max. unit dc characteristics v ih input voltage v cc = gnd pcx, pcy, dnx, dny -1.0 v v il -1.6 v v ih v cc = +5v pcx, pcy, dnx, dny 2.0 v v il 0.8 v i ih input current pcx, pcy, dnx, dny figure 3 5 m a i il -1 +1 m a v ih input voltage rse figure 7 -0.4 v v il -4.0 v v ih tn1 figure 6 -1 v v il -4.5 v v oh output voltage pck r p = 1k w -0.8 v v ol -1.6 v v oh lst i oh = -10 m a, i ol = +10 m a figure 5 -1.0 v v ol -4.0 v v oh sx, sy r p = 220 w -1.6 v v ol -2.4 v ac characteristics f max1 vco max. oscillation frequency 1 rse = "h" figure 4 30.0 mhz f min1 vco min. oscillation frequency 1 14.0 mhz f max2 vco max. oscillation frequency 2 rse = "l" 15.0 mhz f min2 vco min. oscillation frequency 2 10.0 mhz f hp1 pll pull in range f signal = 270mhz rse = "h" figure 1 27.7 mhz f lp1 25.5 mhz f hp2 f signal = 177mhz rse = "h" 18.8 mhz f lp2 16.5 mhz f hp3 f signal = 143mhz rse = "h" 15.0 mhz f lp3 13.0 mhz f op1 pll generator frequency rse = "h" 14.0 27.0 mhz f op2 rse = "l" 10.0 14.5 mhz tjit jitter f signal = 270mhz rse = "h" figure 8 0.25 nsec tested thro ugh pck : 1/10 of serial clock. 1601a-07.tbl switching characteristics (v ee = -5v, v cc = gnd/+5v, t a = 25 o c unless otherwise speciied) symbol parameter test conditions test circuit min. typ. max. unit t r rise time pck r p = 1k w figure 10 0.8 nsec t f fall time 1.4 nsec t r rise time sx, sy r p = 220 w 0.7 nsec t f fall time 0.7 nsec 1601a-08.tbl timing relation of input clock and data symbol parameter test conditions test circuit min. typ. max. unit t w pulse width pcx, pcy figure11 -5 + t c /2 t c /2 +5 + t c /2 nsec t d delay time pcx - dn -5 +5 nsec 1601a-09.tbl STV1601A 6/17
hp8180a signal generator 30 31 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 d0y d0x d1y d1x d2y d2x d3y d3x d4y d4x d5y d5x d6y d6x d7y d7x d8y d8x d9y d9x pcx pcy 25 32 29 27 26 gnd v cc v ee 0.1 10/16v 0.1 10/16v 37 33 28 n.c. 35 -5v -5v -5v sw1 sw2 a b 10 m f/10v 22k w a b high range low rang e vco range select on : af frequency adjust 150pf 0.22 m h 34 trp tn1 -5v 36 pck 1k w frequency monitor 1 lst 3 4 220 w 220 w -5v 0.1 220 w sx sy d.u.t. STV1601A 0.1 vco frequency adjust 10k w v r1 0.1 220 w -5v 220 w 0.1 0.1 0.1 -5v 0.1 0.1 220 w 150 w 150 w 75 w 75 w 1 2 serial out v r v cc e e v -5v input level ttl ec l +1.4v -1.3v +5v gnd stv1389aq pll lock detec tor 33 34 dix diy 220 w 0.1 -5v 220 w 220 w 25 26 28 aiy aix qfs 73 w 41pf 41pf mon 31 100 w a b serial in cx 29 ads 32 sw2 -5v 10k w sy sx 4 3 2 gnd v ee 0.1 0.1 10/16v 24 27 30 23 8 7 -5v a b input select cable input digital input stv1602a -5v vco frequency adjust 10k w fv 36 v r2 eso esi rse 22 1 37 dpr 35 -5v 0. 1 20 syn evr pck d0 d1 21 19 18 17 -5v 0.1 1k w x 4 trs detector signal freqency monitor d2 d3 d4 d5 d6 d7 d8 d9 16 15 14 13 12 11 10 9 1k w x 8 22k w tn1 100k w qsw 6 5 sw3 10 m f -5v 0. 1 led 330 w on : af frequency adjust hp8182a signal analyzer fv rse 10 m f 1601a-11.eps figure 1 : test circuit diagram example STV1601A 7/17
2532 29 a a 27 26 30 3 4 35 28 33 pcx sx sy fv rse tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v -5v sw1 sw1 on position 0.1 m f 220 w 220 w 1k w 10/16v 10/16v 0.1 0.1 ee i cc i ee v -5v cc v +5v STV1601A 1601a-12.eps figure 2 2532 29 27 26 30 3 4 35 28 33 pcx sx sy fv rse tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v -5v sw1 position 0.1 m f 220 w 220 w 1k w 10/16v 0.1 STV1601A -5v 30 31 pcx pcy 11 12 v 2 v 1 sw2 on sw2 -5v a b a1 a2 i il i ih i il i ih v 1 v 2 sw1 any -0.8v -1.6v -1.6v -0.8v 1601a-13.eps figure 4 STV1601A 8/17
2532 29 27 26 30 3 4 35 28 33 pcx sx sy fv rse tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v -5v sw1 position 0.1 m f 220 w 220 w 1k w 10/16v 0.1 STV1601A -5v sw2 on sw2 -5v a b frequency monitor a on b high low sw1 vco range 1601a-14.eps figure 4 2532 29 27 26 35 28 33 fv rse tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v sw1 position 10/16v 0.1 STV1601A -5v 30 31 pcx pcy v 2 v 1 sw2 sw2 -5v a b v 1 v 2 v oh v ol v sw1 off 1 lst v any -0.8v -1.6v -1.6v -0.8v 1601a-15.eps figure 5 STV1601A 9/17
2532 29 27 26 28 33 fv rse gnd v cc ee v v r1 10k w -5v 10/16v 0.1 STV1601A -5v 30 31 pcx pcy v 1 1 lst v tn1 31 -0.8v -1.6v 1601a-16.eps figure 6 2532 29 27 26 30 3 4 35 33 pcx sx sy fv tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v -5v 0.1 m f 220 w 220 w 1k w 10/16v 0.1 STV1601A -5v sw2 frequency monitor 28 rse v 1 1601a-17.eps figure 7 2532 29 27 26 30 3 4 35 33 pcx sx sy fv tn1 gnd v cc ee v v r1 10k w 22k w 10 m f -5v -5v -5v 0.1 m f 1k w 10/16v 0.1 STV1601A -5v sw2 frequency monitor 28 rse -5v 220 w 220 w 220 w 0.1 -5v 0.1 m f 150 w 150 w 0.1 0.1 75 w 75 w 1 2 stv1389aq parallel clock data trigger signal serial out signal 270mb/s jitter = 1/2 t 1601a-18.eps figure 8 STV1601A 10/17
80% 20% tt rf 1601a-19.eps figure 9 : t r , t f definition 50% t c t d t w c t /2 c t /2 1601a-20.eps figure 10 : t d , t w definition description STV1601A internally generates a 10 times clock frequency locked to the parallel input clock thanks to a built-in pll and converts input parallel data into serial data. to ease clock extraction at the receiving end, serial data is scrambled. to minimize polarity effect, serial data is then converted to nrzi and output in differ- ential mode. a pll lock detection circuit only enables the serial output when locked. 1. phase relation between input parallel clock and data the phase relation between the parallel clock and the data is shown in figure 11. both clock and data are differential inputs parallel clock and data are such that the rising edge of pcx should be at the middle of the data. a clock having the same phase as pcx is internally gener- ated in order to latch the data. 2. ttl input operation parallel clock and data can be either ttl or ecl inputs. to use as ttl inputs vcc (pin 29) shall be connected to +5v. a fixed bias of +1.4v shall be applied to pcy and dny (n = 0 to 9). ttl signals and their parallel clock will be provided through 1kw resistors to each "x" input. these 1kw resis- tors are effective to minimize the influence of the ttl input signals to the jitter characteristics of the serial output signal. for 8-bit data, unused lsb(s) must be fixed low. fixed bias value can be higher, for example, 2.5v in case of cmos inputs. pcx (input) data (input) pcx (output) 1601a-21.eps figure 11 : phase relation between clock and data 29 30 31 5 7 26 25 parallel clock parallel data + 5v + 1.4v for ttl + 2.5v for cmos d0y d0x d9y d9x pcy pcx v cc ttl parallel signal STV1601A 1k w 1k w 1k w 1601a-22.eps figure 12 : ttl input operation STV1601A 11/17
3. pll block parallel clock input control pll, pll lock detection and the various blocks of the serial output control are shown in figure 13. when tn1 is connected to gnd (set high), the parallel clock input is disabled. the vco turns to free running conditions and its frequency can be adjus ted through fv. this frequency decreases when the resistor v alue between fv and v ee is reduced. oscillation fre- quency monotoring is performed through pck which delivers a frequency divided by ten. when pll is locked, pll and pcx input signal phases are nearly matched. the rc network con- nected to tn1, temporarily, disables the parallel clock in order to avoid mislocking problems. vco oscillation frequency range selection is avail- able through rse ; high : from 140 to 270mhz ; low : from 100 to 145mhz. trp (pin 34) is the phase comparator output. to minimize jitter, a trap circuit, consisting in a serial tuned circuit at parallel clock frequency can be used. pll lock detection the lst signal is generated by latching the incom- ing parallel clock by the internal one (which is 1/10 of the vco frequency). lst is used as a pll lock detection signal and also controls the serial output. if the parallel clock input is disabled (by means of tn1), lst turns low and the serial output is dis- abled as described in the previous section (sx (pin 3) = high, sy (pin 4) = low). if the serial output has to be disabled while no parallel clock input is provided, pcx must be set low and pcy must be set high. 4. sync word to convert serial data back to parallel, insertion of some timing reference data indicating the parallel data word boundary in the serial data is needed. this, called trs (timing reference signal) in the digital interface format, consists of the three con- secutive words 3ffh, 000h, 000h. conversion to 10-bit trs from 8-bit (trs) 8-bit parallel data 8-bit parallel data can be converted into 10-bit data by using the 8th bit as the msb and by setting the 2 lsbs at logical states as shown in figure 14. lst sx sy serial clock pcy pcx tn1 fv trp rse pck phase comparator vco 1/10 divider nrz to nrzi conversion scrambler q d q d "0" 1601a-23.eps figure 13 : pll and serial output control block STV1601A 12/17
25 d0y d0x v STV1601A 24 23 22 d1x d1y ee 621 8-bit parallel data 10k w 1601a-24.eps figure 14 : 8-bit parallel input data (ecl level) the conversion algorithm detects 2 successive 000h words and sets the two lsbs of the previous word, which is supposed to be ff, according to the standard. 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 input data fixed data 001 001 001 001 001 001 001 001 00 00 1 1 msb lsb input order parallel data after conversion input parallel data 0 1601a-25.eps figure 10 : conversion from 8-bit trs to 10-bit trs conversion in the case of more than three succes - sive "000h" words. if more than 3 consecutive words of 000 in d1 standard, or 4 consecutive words of 000 in d2 standard occur at the parallel input (illegal accord- ing to the standard), thus no proper operation is possible. 5. scrambling and nrz to nrzi conversion figures 16 and 17 show the scrambling circuit, the scrambling polynomial is as follows : x 9 + x 4 + 1. d1 d2 d3 d4 d5 d6 d7 d8 d9 1601a-26.eps figure 16 : (x 9 + x 4 +1) basic scrambling circuit d1 d2 d3 d4 d5 d6 d7 d8 d9 1601a-27.eps figure 17 : (x 9 + x 4 +1) basic scrambling circuit to eliminate signal polarity of scrambled data, con- version from nrz to nrzi is performed (figures 18 and 19). therefore, the polarity for output distribution or receiving is not needed. this allows easy system design. the nrz to nrzi polynominal is x + 1. vco temperature compensation and oscillation frequency adjustment vco oscillation frequency depends on the tem- perature as shown in figures 22 and 23 "repre- sentative characteristics examples". within the normal range of operation, frequency increases with temperature. fv voltage remains almost con- stant regardless of temperature. figure 20 shows an example of a temperature compensation circuit using a diode (transistor with c-b diode short-cir- cuited) and a resistor connected between fv and v ee . examples of representative characteristics for various temperatures are shown in figures 22 and 23 concerning oscillation frequency and pll pull-in range (signal frequency 270, 177 and 143mhz). vco free running frequency adjustment vco free running frequency adjustment is per- formed at room temperature. if tn1 is set high, vco free runs. wait for 5 to 10 minutes after turning power supply on (warm up time). while monitoring pck output (pin 36) adjust the signal frequency (within 1%) with the variable resistor connected between fv and v ee . STV1601A 13/17
jitter trap since the inter nally generated serial clock is locked to the incoming parallel clock, there exists periodic jitter components which are generated from the phase comparison process of the pll. a serial resonant circuit (trap) connected bet ween trp (pin 34) and v ee tuned at the parallel clock frequency reduces effectively the fundamental component of the jitter well below the specification ( 0.25ns). recommended values of c1 and l1 are given in the following table. recommended values of the trap circuit component standard d1 d2 pal ntsc c1 (pf) 150 240 300 l1 ( m h) 0.2 0.3 0.4 an important remark in a practical implementation is that trp node is an input of a very sensitive voltage-frequency converter (vco) which can be easily disturbed by any pick-up noise. hence, the trap circuit should be carefully located and be kept as short as possible from the pin 34 in order to avoid noise problems. v ee STV1601A 10k w tn1 35 33 36 fv small signal transistor frequency monitor 10 m f 22k w 1k w pck trp 34 c1 l1 1601a-30.eps figure 20 : vco temperature compensation and free running adjustment time scale nrzi signal nrz signal nrzi signal nrzi inverted signal nrz to nrzi conversion nrz to nrzi conversion 1601a-29.eps figure 19 : relation between nrz and nrzi signals STV1601A 14/17
37 36 35 34 33 32 31 30 n.c. pck tn1 trp fv gnd pcy pcx -5v -5v 22k w 1k w 10 m f/16v c1 l1 q1 10k w 4.7k w 2.2k w 51 w 51 w 0.1 0.1 -5v 29 28 rse v cc v ee v ee 26 27 high low d0y d0x d1y d1x d2y d2x d3y 25 24 23 22 21 20 19 18 10 17 16 15 14 13 12 11 d7x d7y d6x d6y d5x d5y d4x d4y d3x 1 2 3 4 5 6 7 8 9 d8y d8x d9y d9x gnd sy sx gnd lst parallel data in (ecl balanced pair) c1 l1 d2 pal unit 151 210 0.2 300 0.4 d1 0.3 recommended values -5v 0.1 m f 220 w 220 w 220 w 0.1 m f 0.1 m f -5v -5v 150 w 150 w 220 w 220 w 0.1 m f 0.1 m f 1k w 68 w 68 w parallel clock in test jumper parallel clock test ponit (return) (rate select) -5v ((115ma typical) ntsc m h for signal processig for coaxial cable processing nf STV1601A (encoder module) stv1389aq d2 ntsc d1, d2 pal 10k w 1601a-31.eps figure 21 : application circuit example STV1601A 15/17
0.80 0.90 1.00 1.10 1.20 1.30 300 260 220 180 140 fv pin voltage (v) vco oscillation frequency (mhz) rse: "h" 85?c 65?c 45?c 25?c 5?c -15?c 1601a-32.eps figure 22 : vco oscillation frequency versus fv pin voltage example of representative characteristics 0.90 1.00 1.10 1.20 1.30 fv pin voltage (v) vco oscillation frequency (mhz) 100 110 120 130 140 150 85?c 65?c 45?c 25?c 5?c -15?c rse : "l" 1601a-33.eps figure 23 : vco oscillation frequency versus fv pin voltage -155 25456585 ambient temperature (?c) 30 29 28 27 26 25 24 23 frequency (mhz) high pull in free run low pull in 1601a-34.eps figure 24 : pull in range and free run fre- quency (270mb/s) -155 25456585 ambient temperature (?c) 18 17 16 15 14 13 12 11 frequency (mhz) high pull in free run low pull in 1601a-36.eps figure 26 : pull in range and free run fre- quency (143mb/s) -155 25456585 ambient temperature (?c) 21 20 19 18 17 16 15 14 frequency (mhz) free run high pull in low pull in 1601a-35.eps figure 25 : pull in range and free run fre- quency (177mb/s) STV1601A 16/17
bottom view 25.4 0.5 0.46 0.05 1.2 0.1 25.4 0.5 3.8 1.15 0.15 4.2 seating plane 0.2 2.54 x 9 = 22.86 0.25 pin 28 pin 19 pin 36 pin 10 pin 1 pin 37 2.54 2.54 2.032 max. 2.54 x 9 = 22.86 0.25 dimensions in mm pm-pga37.eps package mechanical data 37 pins - ceramic pga information furnished is believed to be accurate and rel iable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - it aly - ja pan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV1601A 17/17

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